HC2510c 1 HC2510c features l phase - locked loop clock distribution for synchronous dram applications l supports pc - 100 and meets ? pc100 sdram registered dimm specification rev. 1.2 ? l distributes one clock input to one bank of ten outputs l no external rc network required l external feedback (fbin) pin is used to synchronize the outputs to the clock input l separate output enable for each output bank l operates at 3.3 v v cc l 125 mhz maximum frequency l on - chip series damping resistors l support spread spectrum clock(ssc) synthesizers l esd pro tection exceeds 3000 v per mil - std - 883, method 3015 ; exceeds 350 v using machine model ( c = 200 pf, r = 0 ) l latch - up performance exceeds 400 ma per jesd 17 l packaged in plastic 24 - pin thin shrink small - outline package pin configuration general descr iption the HC2510c is a low - skew, low jitter, phase - locked loop(pll) clock driver, distributing high frequency clock signals for sdram. the HC2510c operates at 3.3v v cc and provides integrated series - damping resistors that make it ideal for driving point - to - point loads. the propagation delay from the clk input to any clock output is nearly zero. ten outputs provide low - skew and low - jitter clocks. all outputs can be enabled or disabled via the control input(g). output signal duty cycles are adjusted to 5 0 percent, independent of the duty cycle at clk. the HC2510c is specially designed to interface with high speed sdram applications in the range of 25mhz to 125mhz and includes an internal rc network which provides excellent jitter characteristics and elim inates the needs for external components. for the test purpose, the pll can be bypassed by strapping av cc to ground. the HC2510c is characterized for operation from 0 c to 85 c. function table inputs outputs 1y g clk (0:9) fbout x l l l l h l h h h h h tssop 24 package (top view) agnd vcc 1y0 1y1 1y2 gnd gnd 1y3 1y4 vcc g fbout clk avcc vcc 1y9 1y8 gnd gnd 1y7 1y6 1y5 vcc fbin 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
HC2510c 2 functional block diagram 11 24 13 2 3 3 4 5 8 9 16 17 20 21 12 pll g clk fbin av cc 1y1 1y4 1y7 1y8 1y9 fbout 1y0 1y3 15 1y5 1y6 1y2
HC2510c 3 table 1. pin description pin name pin no. type functional description clk 24 i clock input. clk provides the reference signal to the internal pll. fbin 13 i feedback input. fbin provid es the feedback signal to the internal pll. g 11 i output bank enable. when g is high, all outputs 1y(0:9) are enabled. when g is low, outputs 1y(0:9) are disable to a logic - low state. fbout 12 o feedback output. fbout completes the feedback loop of the pll by being wired to fbin. 1y(0:9) 3,4,5,8,9 15,16,17,20,2 1 o clock outputs. these outputs provide low - skew copies of clkin. each output has an embedded series - damping resistor. av cc 23 power analog power supply. av cc provides the power reference for th e analog circuitry. av cc can be also used to bypass the pll for the test purpose. when av cc is strapped to ground, pll is bypassed and clk is buffered directly to the device outputs. agnd 1 groun d analog ground. agnd provides the ground reference for th e analog circuitry. v cc 2,10,14,22 power power supply gnd 6,7,18,19 groun d ground table 2. absolute maximum ratings over operating free - air temperature range symbols parameter value unit conditions v cc supply voltage range - 0.5 to 4.6 v v i input voltage range - 0.5 to 6.5 v v o voltage range applied to any input in the high or low state - 0.5 to vcc+0.5 v i ik input clamp current 50 ma v i <0 or v i >v cc i ok output clamp current 50 ma v o <0 or v o >v cc i o continuous output current 50 ma v o =0 to v cc p max maximum power dissipaiton 0.7 w t stg storage temperature range - 65 to 150 c
HC2510c 4 table 3. recommended operating conditions value symbol parameter min max unit condition av cc supply voltage 3 3.6 v v ih high - level input voltage 2 v v il low - level input voltage 0.8 v v i input voltage 0 v cc v i oh high - level output current - 12 ma i ol low - level output current 12 ma t a operating free - air temperature 0 85 c table 4. electrical characteristics over recommended operating free - a ir temperature range value symbol min typ max unit av cc (v) test conditions v ik - 1.2 v 3 i i = - 18ma vcc - 0.2 min to max i oh = - 100 m a 2.1 3 i oh = - 12 ma v oh 2.4 v 3 i oh = - 6 ma 0.2 min to max i ol =100 ma 0.8 3 i ol = 12 ma v ol 0.55 v 3 i ol = 6 ma i i 5 m a 3.6 v i =v cc or gnd i cc 10 m a 3.6 v i =v cc or gnd, i o = 0, ouputs: low or high d i cc 500 m a 3.3 to 3.6 one input at v cc - 0.6v, other inputs at v cc or gnd c i 4 pf 3.3 v i = v cc or gnd c o 6 pf 3.3 v o = v cc or gn d table 5.timing requirements over recommended ranges of supply voltage and operating free - air temperature value symbol parameter min max unit f clock clock frequency 25 125 mhz input clock duty cycle 40 60 % stabilization time 1 ms time to obtain phase lock of its feedback signal to it s reference signal.
HC2510c 5 table 6. switching characteristics over recommended ranges of supply voltage and operating free - air temperature. (c l =30 pf ) = v cc = 3.3v 0.165v v cc = 3.3v 0.3v parameter from(input) to(output) min typ max min typ max unit 66mhz < clkin - < 100mhz fbin - 150 150 ps t phase error clkin - = 100mhz fbin - - 50 50 ps t sk any y of fbout any y or fbout 200 ps jitter (pk - pk) clkin > 66mhz any y or fbout - 100 100 ps duty cycle clkin > 66mhz any y or fbout 45 55 % t r any y or fbout 1.3 1.9 0.8 2.1 ns t f any y or fbout 1.7 2.5 1.2 2.7 ns = these parameters are not production tested. phase error does not include jitter . figure 1. load circuit and vo ltage waveforms notes: 1. all input pulses are supplied by generators having the f ollowing characteristics : prr 100mhz, z o =50 w , t r =1.2ns, t f =1.2ns 2.the outputs are measured one at a time with one transition per measurement. 30pf 500 ? from output under test input output 50% v cc 50% v cc 3v 0v v oh v ol t pd 0.4v 0.4v t r t f 2v 2v load circuit for outputs voltage waveforms propagation delay times
HC2510c 6 figure 2. phase error and skew calculation clkin fbin t phase error any any t sk fbout any t sk
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